Inter-computer and intra-computer communications are often characterized by burst mode data transmissions. Conventional ac-coupled optical receivers, intended for continuous data transmission, are usually employed. Undesirably, however, data encoding increases system complexity and reduces the effective data transmission speed. By contrast, high-speed, dc-coupled receivers, while ideally suited for burst mode operation, have proven difficult to implement because of the necessity of establishing a logic reference voltage V.sub.REF level within a few millivolts of the dc center (one-half of the sum of the minimum and maximum excursions of the data signal) of the received data pulse.
When a digital data signal from a data link is received by a preamplifier of a dc-coupled receiver the signal has been degraded to an analog-type signal with uncertain amplitude and non-zero transition times between the logic ZERO and logic ONE levels. Ideally, the dc center of the preamp output should match the logic threshold of the decision circuit so that the decision circuit can restore the analog-type signal to a clean digital signal. When the dc center at the preamp output does not match the logic threshold, the decision circuit causes pulse-width distortion (PWD) or may not be able to detect a logic transition. This PWD is undesirable because it reduces the sensitivity and maximum bandwidth of the system. The problem is additionally complicated by the fact that input data amplitudes can vary by factors of 100 or more.
Thus it is a continuing problem to design a burst mode digital data receiver with minimized PWD and increased sensitivity.